The JESD204B Transmitter IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The JESD204B Transmitter IIP can be implemented in any technology.

The JESD204B Transmitter IIP core supports the JESD204B.01 standard. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB, Wishbone  or  custom buses.

The JESD204B Transmitter IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The JESD204B Transmitter IIP is validated in using FPGA. The Transmitter core includes RTL code, test scripts and a test environment for complete simulation.